1. Field of the Invention
The present invention relates to a DMA controller that controls the transfer of data performed between peripheral devices without the intervention of a central processing unit (hereinafter abbreviated to xe2x80x9cCPUxe2x80x9d).
2. Description of the Prior Art
When a DMA controller receives a request for data transfer from a peripheral device, it requests access to a system bus from a CPU. When the DMA controller is permitted access to the system bus, it starts transferring data from a predetermined source location to a predetermined destination location. As opposed to data transfer controlled by a CPU, in data transfer controlled by a DMA controller (hereinafter referred to as xe2x80x9cDMA transferxe2x80x9d), there is no need to read and interpret commands, and this makes fast data transfer possible. A DMA controller has a count register to which a CPU writes the number of data transfer cycles to be performed, so that the DMA controller ends DMA transfer when it has performed as many data transfer cycles as written to the count register.
However, a conventional DMA controller is provided with, for each channel, only one register to which a CPU writes the information on the number of data transfer cycles. Thus, in response to a single request for DMA transfer, either a single cycle or a specified number of cycles of DMA transfer can only be performed. Therefore, in a case where a plurality of DMA transfer cycles are performed in response to a single DMA transfer request, and a plurality of DMA transfer requests are made in succession, every time a DMA transfer request is made, the CPU needs not only to set the DMA controller to perform a specified number of DMA transfer cycles in response to a single DMA transfer request, but also to set in the DMA controller the addresses of the source and destination locations and the number of transfer cycles to be performed. This lowers overall system performance.
An object of the present invention is to provide a DMA controller that operates with reduced lowering of overall system performance in a case where a predetermined number of DMA transfer cycles are performed in response to a single DMA transfer request and a plurality of DMA transfer requests are made in succession.
To achieve the above object, according to the present invention, a DMA controller is provided with: a cycle register in which the number of data transfer cycles to be performed in response to a single DMA transfer request is set; a cycle counter for counting the number of data transfer cycles actually performed; and a transfer counter for holding a value that is updated every time the number of data transfer cycles as held in the cycle register are completed. Here, from the start to the end of the data transfer cycles, the number held in the cycle register is kept unchanged, and the data transfer cycles are performed until the value held in the transfer counter becomes equal to a predetermined value.
In this configuration, even in a case where a predetermined number of DMA transfer cycles are performed in response to a single DMA transfer request and a plurality of DMA transfer requests are made in succession, the CPU has to set in the DMA controller only once the addresses of the source and destination locations and the values to be held in the cycle register and the transfer counter. Specifically, the value to be held in the cycle register is set according to the number of DMA transfer cycles to be performed in response to a single DMA transfer request, and the value to be held in the transfer counter is set according to the number of DMA transfer requests that are made in succession. In this way, the conditions under which to perform DMA transfer can be set all together. This helps alleviate the burden on the CPU and thereby accordingly reduce the lowering of overall system performance.